Gary Grewal
Gary Grewal
Associate Professor
School of Computer Science
University of Guelph, Guelph, ON   N1G 2W1
Office:MacLachlan 218
Phone:1-519-824-4120 ext. 52630

IronTracker Mobile App

In 2011, I was diagnosed with Hereditary Hemochromatosis (HHC), a genetic disorder that casues too much iron to accumulate in organs like the liver, pancreas, heart and even the brain. Without early detection and treatment, HHC can lead to diabetes, organ failure and early death. However, if caught early, treatment is relatively straightforward and involves blood monitoring and regular phlebotomies for life. Despite being the most common genetic disorder in Canada, affecting approximately 1 in 300 Canadians, it is estimated that 80 percent of Canadians who have the disorder do not know that they do! To help remedy this problem, I worked with colleague Andrew Hamilton-Wright and several excellent students (A. D'Angelo, J. Carter, F. Liu and R. Pattison) in conjunction with the Canadian Hemochromatosis Society to develop a mobile application, called IronTracker. The mobile app was not only designed to bring awarenenss to HHC, but to assist those who suffer with HHC manage their de-ironing treatments. The mobile app is available in English, French, Portugese, and Italian, and has been downloaded by people from over 100 countries. In 2015, members of the app's development team were recognized at Parliament Hill, by Senator David Wells, and in the Ontario Legislature, by MPP Chris Ballard. IronTracker was also higlighted in various media including newspaper and magazine articles, as well as radio and television interviews. More information about HHC can be foundat the Canadian Hemochromatosis website. The app is available from Google Play or from the App Store.


StarPlace is a Field Programmable Gate Array (FPGA) analtyic placement tool. FPGAs are reprogrammable chips that can implement a wide range of digital circuits. In the process of mapping a digital circuit onto an FPGA, a very important, but time-consuming problem, called placement, must be solved. The input to the placement problem is a circuit netlist specifying the various types of logic blocks to be implemented and the interconnections between them. The result of placement is the mapping of all blocks onto physical resources on the target FPGA in a way that minimizes one or more objectives. StarPlace seeks to minimize the two most basic objectives: total wirelength and critical-path delay. When compared to VPR -- the state of the art academic placer -- StarPlace obtains an 8-9% reduction in critical-path delay while achieving a speedup of nearly 5x when VPR is run in its "fast" mode. StarPlace Download